Developing a configurable architecture for an inkjet heater chip allows for multiple applications of the design as well as more opportunities for Original Equipment Manufacturer (OEM) vendors. One of the fundamental specifications of a chip is the number of required data input pads and the rate at which serial data is clocked to the chip. These design variables are inversely related; reducing the number of inputs would require an increase in the clock rate in order to transfer the same amount of data.
In a consumer printer application where minimizing printer cost is a design goal, it would be advantageous to use the traditional method of serial communication from the print engine to a passive carrier card along a ribbon cable. The resistive and capacitive nature of the ribbon cable itself limits the rate at which data can be reliably transmitted. For this case, supporting more inputs at a slower clock rate may be the optimal design point.
In certain OEM applications like a large format plotter, multiple printheads may be used in a staggered configuration to achieve the necessary print speeds. For this type of system, performance may be the primary design goal with plotter cost being secondary. In this case, data can be transferred from a print engine to a carrier card with a local digital ASIC capable of driving multiple heads. For this configuration, the cable distance is minimized so it is desirable to increase the data rate while reducing the number of outputs required by the local ASIC. In past heater chip designs the clock rate and number of inputs has been fixed.